7 commits

Author	SHA1	Message	Date
Gustavo Stingelin	0176e96e3c	staticaddr: generate FSM diagrams	2026-07-20 12:07:26 -03:00
Gustavo Stingelin	e77a1ab634	fsm: harden diagram generation	2026-07-20 12:07:26 -03:00
Gustavo Stingelin	1d5b1c564a	fsm: make diagram generation deterministic	2026-07-18 16:27:11 -03:00
sputn1ck	56848d0cfa	reservation: add protocol version	2025-04-30 14:23:47 +02:00
sputn1ck	f725f07dd9	fsm: add instanout fsm parsing	2024-02-06 15:08:00 +01:00
sputn1ck	9b178dd979	fsm: add reservation fsm compiling	2024-01-17 15:59:09 +01:00
sputn1ck	20db07dccf	fsm: add fsm module ... This commit adds a module for a finite state machine. The goal of the module is to provide a simple, easy to use, and easy to understand finite state machine. The module is designed to be used in future loop subsystems. Additionally a state visualizer is provided to help with understanding the state machine.	2023-09-07 17:41:15 +02:00