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3 commits

Author SHA1 Message Date
Gustavo Stingelin
1d5b1c564a fsm: make diagram generation deterministic 2026-07-18 16:27:11 -03:00
sputn1ck
f725f07dd9
fsm: add instanout fsm parsing 2024-02-06 15:08:00 +01:00
sputn1ck
20db07dccf
fsm: add fsm module 
This commit adds a module for a finite state machine. The goal of the
module is to provide a simple, easy to use, and easy to understand
finite state machine. The module is designed to be used in future
loop subsystems. Additionally a state visualizer is provided to
help with understanding the state machine.
 2023-09-07 17:41:15 +02:00